This application is related to the following co-filed and commonly assigned applications: Ser. No. 09/488,098 entitled xe2x80x9cMethod and Apparatus for Making Integrated-Circuit Wiring from Copper, Silver, Gold, and Other Metals,xe2x80x9d and Ser. No. 09/484,303 entitled xe2x80x9cMethod for Making Copper Interconnects in Integrated Circuits,xe2x80x9d which are hereby incorporated by reference. This application is further related to the following co-pending and commonly assigned application: U.S. Ser. No. 09/128,859 filed Aug. 9, 1999, entitled xe2x80x9cCopper Metallurgy in Integrated Circuits,xe2x80x9d which is hereby incorporated by reference.
The present invention relates generally to integrated circuits. More particularly, it pertains to structures and methods for providing seed layers for integrated circuit metallurgy.
One of the main problems confronting the semiconductor processing industry, in the ULSI age, is that of Capacitive-Resistance loss in the wiring levels. This has led to a large effort to reduce the resistance of and lower the capacitive loading on the wiring levels. Since its beginning, the industry has relied on aluminum and aluminum alloys for wiring. In a like manner, the industry has mainly relied on SiO2 as the insulator of choice, although polyimide was used in a number of products by one vendor (IBM), for a number of years. The capacitive resistance problem grows with each succeeding generation of technology. As the dimensions decrease the minimum line space combination decreases, thus increasing both capacitance and resistance, if the designer is to take advantage of the improved ground rules.
To improve the conductivity, it has been suggested by numerous investigators, that copper or perhaps silver or gold metallurgy be substituted for the aluminum metallurgy, now being used. Several potential problems have been encountered in the development of these proposed metallurgies. One of the main ones is the fast diffusion of copper through. both silicon and SiO2. This along with the known junction poising effects of copper and gold have led to proposals to use a liner, to separate these metallurgies from the SiO2 insulator.
For example, an article authored by Karen Holloway and Peter M. Fryer, entitled, xe2x80x9cTantalum as a diffusion barrier between copper and siliconxe2x80x9d, Appl. Phys. Letter vol.57, No. 17, 22 October 1990, pp. 1736-1738, suggests the use of a tantalum metal liner. In another article authored by T. Laursen and J. W. Mayer, entitled, xe2x80x9cEncapsulation of Copper by Nitridation of Cuxe2x80x94Ti Alloy/Bilayer Structuresxe2x80x9d, International Conference on Metallurgical Coatings and Thin Films, San Diego, Calif., Apr. 21-25, 1997, Abstract No. H1.03, pg. 309, suggests using a compound such as CuTi as the liner. Still another article published by Vee S. C. Len, R. E. Hurley, N. McCusker, D. W. McNill, B. M. Armstrong and H. S. Gamble, entitled, xe2x80x9cAn investigation into the performance of diffusion barrier materials against copper diffusion using metal-oxide-semiconductor (MOS) capacitor structuresxe2x80x9d, Solid-State Electronics 43 (1999) pp. 1045-1049 suggests using a compound such as TaN as the liner. These approaches, however, do not fully resolve the above-stated problem of the minimum line space decreases. Thus, the shrinking line size in the metal line and liner combination again increases both the. capacitance and resistance.
At the same time other investigators, in looking at the capacitive loading effect, have been studying various polymers such as fluorinated polyimides as possible substitutions for SiO2 insulators. Several of these materials have dielectric constants considerably lower than SiO2. However as in the case of SiO2, an incompatibility problem with copper metallurgy has been found. For example, in a presentation by D. J. Godbey, L. J. Buckley, A. P. Purdy and A. W. Snow, entitled, xe2x80x9cCopper Diffusion in Organic Polymer Resists and Inter-level Dielectricsxe2x80x9d, at the International Conference on Metallurgical Coatings and Thin Films, San Diego, Calif., Apr. 21-25, 1997, Abstract H2.04 pg. 313, it was shown that polyimide, and many other polymers, react with copper during the curing process, forming a conductive oxide CuO2, which is dispersed within the polymer. This then raises the effective dielectric constant of the polymer and in many cases increases the polymers conductivity. In addition it has been found that reactive ion etching (RIE) of all three metals, copper, silver or gold, is difficult at best.
Other approaches by investigators have continued to look for ways to continue to use aluminum wiring with a lower dielectric constant insulator. This would decrease the capacitive load with a given inter-line space but require wider or thicker lines. The use of thicker lines would increase the capacitive loading in direct proportion to the thickness increase. Thus to some measure, it defeats the objectives of decreasing the capacitive loading effects. Therefore, the use of thicker lines should be avoided as much as possible. As the resistivity of the line is directly proportional to its cross-sectional area, if it cannot be made thicker, it must be. made wider. If however the lines are made wider, fewer wiring channels can be provided in each metal level. To obtain the same number of wiring channels, additional levels of metal must be provided. This increases the chip cost. So if this approach is to be followed, it is imperative that a low cost process sequence be adopted.
One approach provided by the present inventor in a co-pending application, entitled, xe2x80x9cCopper Metallurgy in Integrated Circuitsxe2x80x9d, filed Aug. 4, 1998, application Ser. No. 09/128,859, proposes a method to solve many of the problems associated with using copper in a polymer insulator. This process, which was specifically designed to be compatible with a polymer or foam insulation, required that the unwanted copper on the surface of each layer be removed by Chemical Mechanical Polishing (CMP) or a similar planarizing process. However, this method may require careful process control, leading to additional expense. Another approach is provided in a co-pending application by Kie Ahn and Leonard Forbes, entitled xe2x80x9cMethod for Making Copper and Other Metal Interconnections in Integrated Circuitsxe2x80x9d, filed Feb. 27, 1998, U.S. Ser. No. 09/032,197, which proposes a method using ionized sputtering to form the underlayer, then forming a low wetting layer on the areas where no copper is desired using jet vapor deposition. The copper is deposited with ionized Magnetron sputtering followed by hydrogen annealing. The excess copper is then removed by CMP as in the aforementioned application.
Another process is described by the present inventor in a co-pending application, entitled, xe2x80x9cIntegrated Circuit with Oxidation Resistant Polymeric Layerxe2x80x9d, filed Sep. 1, 1998, U.S. Ser. No. 09/145,012, which eliminates many of the CMP processes and uses lift-off to define the trench and the seed layer simultaneously. A process is also described by the present inventor in a co-pending. application, entitled, xe2x80x9cConductive Structures in Integrated Circuitsxe2x80x9d filed Mar. 1, 1999, U.S. Ser. No. 09/259,849, which required a CMP process to remove unwanted seed material prior to a selective deposition of the metal layers in a damascene or dual damascene process.
The use of CMP has proven to be effective in reducing local non-planarity. However, extensive dishing in wide lines and rounding of comers of the insulator are a common occurrence. It has been found that by maintaining a regular structure through the use of dummy structures and small feature sizes, it is possible to planarize a level to a nearly flat surface. The use of these techniques are however costly and in some cases come with density or performance penalties. It is, however, generally possible to planarize a structure prior to the metal levels using these methods with little or no density penalty. The use of electroless plating has been suggested in an article authored by Yosi Schacham-Diamand and Valery M. Dubin, entitled xe2x80x9cCopper electroless deposition technology for ultra-large scale integration (ULSI) metallizationxe2x80x9d, Microelectronic Engineering 33 (1997) 47-58, however a simple process for obtaining both a barrier layer as well as a seed layer is needed to improve the cost effectiveness of this technique. One technique for seeding polyimide and silicon surfaces using high energy (10-20 Kilo Electron Volts {KEV}) ion implantation has been demonstrated in an article authored by S. Bhansali, D. K. Sood and R. B. Zmood, entitled xe2x80x9cSelective electroless copper plating on silicon seeded by copper ion implantationxe2x80x9d, Thin Solid Films V253 (1994) pp. 391-394. However this process has not been shown to be implementable into a product structure where a barrier and/or adhesion layer is required.
For the reasons stated above and for others which will become apparent from reading the following disclosure, structures and methods are needed which alleviate the problems associated with via and metal line fabrication processes. These structures and methods for via and metal line fabrication must be streamlined and accommodate the demand for higher performance in integrated circuits even as the fabrication design rules shrink.
The above mentioned problems associated with integrated circuit size and performance, the via and metal line formation process, and other problems are addressed by the present invention and will be understood by reading and studying the following specification. The structures and methods of the present invention include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. According to the teachings of the present invention, the selective deposition of the metal lines avoids the need for multiple chemical mechanical planarization (CMP) steps. The low energy ion implantation of the present invention allows for the distinct placement of both the diffusion barrier and the seed layer. A residual resist can be used to remove the diffusion barrier and the seed layer from unwanted areas on a wafer surface.
In particular one illustrative embodiment of the present invention includes a method of making a diffusion barrier and a seed layer in an integrated circuit. The method includes patterning an insulator material to define a number of trenches in the insulator layer opening to a number of first level vias in a planarized surface. A barrier/adhesion layer is deposited in the number of trenches using a low energy ion implantation, e.g. a 100 to 800 electron volt (eV) ion implantation. A seed layer is deposited on the barrier/adhesion layer in the number of trenches also using the low energy ion implantation. This novel methodology further accommodates the formation of aluminum, copper, gold, and/or silver metal interconnects.
The following detailed description of the preferred embodiments can best be understood when read in conjunction with the following drawings, in which:
FIGS. 1A-1K illustrate one embodiment of the various processing steps for forming vias and metal lines according to the teachings of the present invention;
FIGS. 2A-2K illustrate another embodiment of the various processing steps for forming vias and metal lines according to the teachings of the present invention;
FIGS. 3A-3K illustrate another embodiment of the various processing steps for forming vias and metal lines according to the teachings of the present invention;
FIGS. 4A-4L illustrate another embodiment of the various processing steps for forming vias and metal lines according to the teachings of the present invention;
FIG. 5, is an illustration of an integrated circuit formed according to the teachings of the present invention.
FIG. 6 illustrates an embodiment of a system including a portion of an integrated circuit formed according to any of the embodiments described in the present application.